Freescale Semiconductor /MKL28T7_CORE1 /SCG /FIRCDIV

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Interpret as FIRCDIV

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (000)FIRCDIV1 0 (000)FIRCDIV2 0 (000)FIRCDIV3

FIRCDIV3=000, FIRCDIV1=000, FIRCDIV2=000

Description

Fast IRC Divide Register

Fields

FIRCDIV1

Fast IRC Clock Divide 1

0 (000): Output disabled

1 (001): Divide by 1

2 (010): Divide by 2

3 (011): Divide by 4

4 (100): Divide by 8

5 (101): Divide by 16

6 (110): Divide by 32

7 (111): Divide by 64

FIRCDIV2

Fast IRC Clock Divide 2

0 (000): Output disabled

1 (001): Divide by 1

2 (010): Divide by 2

3 (011): Divide by 4

4 (100): Divide by 8

5 (101): Divide by 16

6 (110): Divide by 32

7 (111): Divide by 64

FIRCDIV3

Fast IRC Clock Divider 3

0 (000): Clock disabled

1 (001): Divide by 1

2 (010): Divide by 2

3 (011): Divide by 4

4 (100): Divide by 8

5 (101): Divide by 16

6 (110): Divide by 32

7 (111): Divide by 64

Links

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